The present invention relates generally to semiconductor processing, and in particular to a system and method for monitoring and regulating the formation of a T-top polysilicon etch (T-top gate structure).
Historically, gate structures with a base area width smaller than a gate contact area (e.g., T-gate and Y-gate structures) have been advantageous to several technologies. For example, MESFET and HEMT (variant of gallium arsenide field effect transistor technology), which are utilized in satellite broadcasting receivers, high-speed logic circuits and power modules, have employed T-gate and/or Y-gate structures. Such devices are employed in field effect transistors to facilitate ultra-high frequency range operation. Employing a gate structure with a shorter gate length reduces the gate channel, with resulting speed increases and power consumption reductions. Such gate structures similarly provide reductions to the parasitic resistances and capacitances that limit device speed. A shorter gate length decreases transmit time for carriers in the channel but also increases series resistance of the gate electrode itself, slowing down the device and degrading the frequency characteristics of the device. Providing a gate structure with a smaller base than its contact area decreases the gate channel while providing a low gate series resistance due to the wider contact area. Decreasing the gate channel while lowering the gate series resistance improves device drive current capability and performance. Thus, providing gates with such features is desired in semiconductor manufacturing. But conventional techniques for fabricating such gates suffer from shortcomings.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these higher densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller features sizes fabricated with more precise patterns are required. This may include the profile of the feature being formed (e.g., T-gate, Y-gate), the slope of a feature face, the depth of a trench being etched, and the surface geometry, such as corners, angles and edges of various features. The requirement of small features with complicated profiles and close spacing between adjacent features requires high-resolution photolithographic processes.
In general, lithography refers to processes for pattern transfer between various media. Lithography is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, (the resist), and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, (the mask), for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble, depending on the coating, in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer, which can subsequently be etched away.
Fabricating T-gate structures can require sophisticated etching. Conventionally, such etching has either not been feedback controlled, requiring precalculated etching properties and/or layer specific etching processes or has had feedback based on indirect information (e.g., amount of gas generated by plasma gas discharge etching). Such pre-determined calculations and/or indirect feedback control may not provide fine enough control for etching processes required for forming T-gate structures. Removing insufficient amounts of the oxide layer and/or removing undesired portions of the oxide layer may result in features that are too large and/or exhibit undesired profiles. Similarly, removing too much of the oxide layer and/or removing undesired portions of the oxide layer may result in features that are too small and/or exhibit undesired profiles.
Recent advances in CMOS transistor architecture employ T-gate or Y-gate structures where the polysilicon gate electrode is narrowed in the gate regions and widened on top of the gate. However, conventional methods for forming a gate structure with a contact region wider than its base suffer from shortcomings. For example, the etch process that narrows the base of the structure is known to be difficult to control, especially with local pattern density. This can lead to variations in the gate width and asymmetric, undesired profiles. Conventional inspection systems such as scanning electron microscope (SEM) do not provide adequate information relating to the dimensions of the T-gate structures.
Due to the extremely fine patterns that are exposed on the photo resist, controlling the etching process, whereby oxide or other materials are removed, is a significant factor in achieving desired feature profiles. Thus, an efficient system, and/or method, to monitor T-top gate formation is desired to facilitate manufacturing ICs with desired feature profiles, which can increase the quality of the underlying wafer being manufactured.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the present invention relates to a method for monitoring T-top gate formation. The method includes providing a wafer structure undergoing a T-top gate fabrication process; generating a signature associated with the wafer structure during a process step to monitor formation of the T-top gate; and comparing the generated signature to a signature store to determine a state of the T-top gate.
Another aspect of the present invention provides an in-line method for determining T-top gate dimensions comprising: providing a wafer structure having a T-top gate formed thereon; generating a signature associated with the T-top gate; comparing the generated signature with a signature store to determine the dimensions of the T-top gate; and if the dimensions of the T-top gate are not within a pre-determined acceptable range, then adjusting T-top gate process parameters using feedback control.
Yet another aspect of the present invention provides An in-line method for determining T-top gate dimensions comprising: providing a wafer structure having a T-top gate formed thereon; directing an incident beam of light at the T-top gate; collecting the reflected light associated with the T-top gate; generating a signature associated with the T-top gate using the reflected light; comparing the generated signature with a signature store to determine the dimensions of the T-top gate; and if the dimensions of the T-top gate are not within a pre-determined acceptable range, then adjusting T-top gate process parameters using feedback control.
Still another aspect of the present invention relates to an in-line system for monitoring T-top gate formation. The system comprises a wafer structure undergoing a T-top gate formation process; a T-top gate formation monitoring system for generating a signature associated with wafer surface dimensions during a process step; and a signature store coupled to the monitoring system, wherein the generated signature is compared to the signature store to determine a state of the T-top gate.
Still another aspect of the present invention relates to An in-line system for determining T-top gate dimensions comprising: a wafer structure undergoing a T-top gate formation process; a scatterometry system coupled to the formation process for directing light at and collecting reflected light from the wafer structure; a signature store comprising known signatures associated with T-top gate formation; a T-top gate formation analysis system coupled to the scatterometry system and to the signature store for determining the T-top gate dimensions; and a feedback control system ret coupled to the T-top gate formation analysis system for optimizing T-top gate formation.
Yet another aspect of the present invention relates to an in-line system for determining T-top gate dimensions. The system comprises means for providing a wafer structure having a T-top gate formed thereon; means for generating a signature associated with the T-top gate; means for comparing the generated signature with a signature store to determine the dimensions of the T-top gate; and if the dimensions of the T-top gate are not within a pre-determined acceptable range, then means for adjusting T-top gate process parameters using feedback control.
To the accomplishment of the foregoing and related ends, certain illustrative aspects of the invention are described herein in connection with the following description and the annexed drawings. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such aspects and their equivalents. Other advantages and novel features of the invention may become apparent from the following detailed description of the invention when considered in conjunction with the drawings.